Conventional design of digital systems involves the selection and assembly of standard integrated circuits (ICs). However, it is often desirable to produce the digital system on a single large scale integrated circuit. If such large scale ICs are designed from scratch, they are referred to as custom chips. Custom chips are quite expensive to create and are usually only justified when the number of chips to be produced is quite large. Another approach is to utilize gate arrays which are sometimes referred to as semicustom chips. Gate arrays consist of a relatively large number of unconnected logic gates laid out in a prearranged pattern on a semiconductor substrate. Designs are implemented by individualizing the connection of these gates in the final metalization step.
Gate arrays have an advantage over custom chips in being relatively inexpensive to build. However, gate arrays typically only have a limited number of elements or cells from which to create a design. For example, many gate arrays have only a single size (fixed channel width and length) p channel transistor and a single size n channel transistor from which to select. Being restricted in the types of transistors available can create certain design problems.
A particular design problem that can arise is with drivers requiring higher or lower output current than available by selectively turning on or off a single transistor connected to a reference voltage. In the past, higher output current has been obtained by connecting a number of transistors in parallel. Similarly, lower current has been obtained by connecting the transistors in series. Series connection of transistors to reduce current can easily require dozens or even hundreds of transistors. This is inherently undesirable due to the large number of devices consumed.
One solution for avoiding series connected transistors is to simply accept higher than desired driver output current. This contributes to substantially increased chip power dissipation with no benefit to the design. An alternative solution is to make different size transistors available on the gate array. There are two ways this has been attempted in the past. One is by intermingling different size transistors in a predetermined layout pattern on the chip. This complicates the design process and can result in increased numbers of unused transistors. Another way is by providing dedicated areas on the chip for the layout of off size transistors. Another way is to provide such transistors in peripheral or pad areas of the gate array chip. This has the disadvantage of requiring the routing of relatively long wires which can waste layout space. It is also limited by the number and size of peripherally placed transistors, thereby reducing flexibility in the design of multiple drive current values.